ACE: Adaptive Compute-Efficient State Space Models
Dynamic token routing for Mamba models that adapts computation to token importance.
Read research overviewElectrical & Computer Engineering · Georgia Tech
Ashiqur Rasul
Making machine learning
compute more efficiently.
I am a Ph.D. student working at the intersection of adaptive machine learning and efficient hardware. My research connects input-aware algorithms with the architectures that run them.
Atlanta, Georgia
About
From adaptive algorithms
to efficient silicon.
I am a Graduate Research Assistant in the Low-power, Adaptive and Resilient Systems (LARS) Lab at Georgia Tech, advised by Prof. Abhijit Chatterjee. I study how models can adapt their computation to each input, and how hardware can turn that adaptivity into practical improvements in efficiency.
My work spans state space models, memory-centric retrieval, sparse neural networks, and testing for compute-in-memory systems. My hardware experience includes a TSMC 65 nm systolic array tapeout and an ongoing sparsity-enabled systolic array project in TSMC 28 nm HPC.
Before Georgia Tech, I earned my B.Sc. at Bangladesh University of Engineering and Technology (BUET) and taught electrical and electronic engineering.
Selected research
Less computation. More possibility.
CASPER: Adaptive Retrieval with In-DRAM Processing
Confidence-guided dimension adaptivity and in-DRAM similarity search for efficient information retrieval.
Read research overviewAdaptive Testing of Compute-in-Memory GANs
Backpropagation-guided test compaction for faster testing of analog compute-in-memory systems.
Read research overviewWriting & collaboration
Selected publications
CASPER: Confidence-Guided Adaptive Nearest Neighbor Search with In-DRAM Processing for Efficient Information Retrieval
Design, Automation & Test in Europe (DATE) 2027 · Under review
ACE: Adaptive Compute-Efficient State Space Models with Dynamic Token Routing
AAAI 2026 · Under review
Adaptive Testing of Compute-in-Memory GANs Using Backpropagation-Guided Test Compaction
Design, Automation & Test in Europe (DATE) 2026
Background
Education
2024–present
Ph.D. in Electrical & Computer Engineering
Georgia Institute of Technology
Hardware–software co-design for adaptive and compute-efficient ML
2024–2025
M.Sc. in Electrical & Computer Engineering
Georgia Institute of Technology · GPA 4.00/4.00
2017–2022
B.Sc. in Electrical & Electronics Engineering
Bangladesh University of Engineering and Technology · GPA 3.89/4.00
Get in touch
Let’s connect.
For research collaborations and opportunities in efficient ML and hardware design.
arasul6@gatech.edu